Scope and project conditions
Design carrier boards around established compute modules, connecting cameras, networking, storage, displays and control interfaces with board-level software adaptation.
The carrier service uses a selected compute module; SoC core-board and DDR design require a separate scope.
Development and delivery process
Requirements and interfaces
Compute-module documentation, BSP version, camera configuration, peripherals, power and mechanical constraints.
Design and implementation
Design carrier boards around established compute modules, connecting cameras, networking, storage, displays and control interfaces with board-level software adaptation.
Integration and validation
Validate power-up, boot, cameras, peripherals, storage I/O, concurrent workloads and temperature rise with software and hardware revisions recorded.
Versioned delivery and handover
Carrier schematics and PCB, BOM, prototypes, device-tree or BSP changes and debug documentation.
Deliverables and version records
Project deliveryCarrier schematics and PCB, BOM, prototypes, device-tree or BSP changes and debug documentation.
At project kickoff, agree prototype quantities, source-file scope, build environment, third-party components and handover method. Deliverables identify their hardware and software revisions for maintenance and future changes.
Validation and acceptance
Service-specific checksValidate power-up, boot, cameras, peripherals, storage I/O, concurrent workloads and temperature rise with software and hardware revisions recorded.
Define the configuration, test objects, operating conditions and decision method before testing. Acceptance records include the setup, raw evidence, issue resolution and retests; performance values come from the corresponding test conditions.
Project questions
What is included in the delivery?
Carrier schematics and PCB, BOM, prototypes, device-tree or BSP changes and debug documentation.
What needs to be agreed before the project starts?
The carrier service uses a selected compute module; SoC core-board and DDR design require a separate scope.